发布时间 : 星期六 文章EDA技术实用教程课后答案 - 潘松-黄继业更新完毕开始阅读5ffc1024541252d380eb6294dd88d0d233d43c35
3-3 给出一个4选1多路选择器的VHDL描述。选通控制端有四个输入：S0、S1、S2、S3。当且
仅当S0=0时:Y=A；S1=0时:Y=B；S2=0时:Y=C；S3=0时:Y=D。 --解：4选1多路选择器VHDL程序设计。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux41a IS
PORT( A,B,C,D : IN STD_LOGIC; S0,S1,S2,S3 : IN STD_LOGIC; Y : OUT STD_LOGIC); END ENTITY mux41a;
ARCHITECTURE one OF mux41a IS
SIGNAL S0_3 : STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN
S0_3<=S0&S1&S2&S3;
y<=A WHEN S0_3=\ B WHEN S0_3=\ C WHEN S0_3=\ D WHEN S0_3=\ 'Z';
END ARCHITECTURE one;
3-4 给出1位全减器的VHDL描述；最终实现8位全减器。要求:
1)首先设计1位半减器,然后用例化语句将它们连接起来,图4-20中h_suber是半减器,diff是输出差
a xin (diff=x-y),s_out是借位输出(s_out=1,x yin b 图3-19 1位全加器 --解(1.1)：实现1位半减器h_suber(diff=x-y；s_out=1,x USE IEEE.STD_LOGIC_1164.ALL; ENTITY h_suber IS PORT( x,y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END ENTITY h_suber; ARCHITECTURE hs1 OF h_suber IS BEGIN Diff <= x XOR (NOT y); s_out <= (NOT x) AND y; END ARCHITECTURE hs1; --解(1.2)：采用例化实现图4-20的1位全减器 LIBRARY IEEE; --1位二进制全减器顺层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_suber IS PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END ENTITY f_suber; ARCHITECTURE fs1 OF f_suber IS COMPONENT h_suber --调用半减器声明语句 PORT(x, y: IN STD_LOGIC; diff,s_out: OUT STD_LOGIC); END COMPONENT; SIGNAL a,b,c: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN u1: h_suber PORT MAP(x=>xin,y=>yin, diff=>a, s_out=>b); u2: h_suber PORT MAP(x=>a, y=>sub_in, diff=>diff_out,s_out=>c); sub_out <= c OR b; END ARCHITECTURE fs1; (2)以1位全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项设计(减法运算是x-y-sun_in=difft)。 x7 y7 a6 x1 y1 xin sub_out yin u7 sub_in diff_out ………………. ………………. xin sub_out yin u1 sub_in diff_out xin sub_out yin u0 sub_in diff_out 串行借位的8位减法器 a1 diff1 diff0 sout diff7 a0 x0 y0 sin --解(2)：采用例化方法，以1位全减器为基本硬件；实现串行借位的8位减法器(上图所示)。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY suber_8 IS PORT(x0,x1,x2,x3,x4,x5,x6,x7: IN STD_LOGIC; y0,y1,y2,y3,y4,y5,y6,y7,sin: IN STD_LOGIC; diff0,diff1,diff2,diff3: OUT STD_LOGIC; diff4,diff5,diff6,diff7,sout: OUT STD_LOGIC); END ENTITY suber_8; ARCHITECTURE s8 OF suber_8 IS COMPONENT f_suber --调用全减器声明语句 PORT(xin,yin,sub_in: IN STD_LOGIC; sub_out,diff_out: OUT STD_LOGIC); END COMPONENT; SIGNAL a0,a1,a2,a3,a4,a5,a6: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN u0:f_suber PORT MAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0); u1:f_suber PORT MAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1); u2:f_suber PORT MAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2); u3:f_suber PORT MAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3); u4:f_suber PORT MAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4); u5:f_suber PORT MAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5); u6:f_suber PORT MAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6); u7:f_suber PORT MAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout); END ARCHITECTURE s8; 3-8 设计一个求补码的程序，输入数据是一个有符号的8位二进制(原码)数。 --解：5-9 设计一个求补码的程序，输入数据是一个有符号的8位二进制数。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY org_patch IS PORT( org_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);--原码输入 patch_data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));--补码输出 END org_patch; ARCHITECTURE BHV OF org_patch IS BEGIN PROCESS(org_data) BEGIN IF(org_data(7)='0') THEN patch_data<=org_data; --org_data>=0，补码=原码。 else patch_data<=org_data(7)&(not org_data(6 DOWNTO 0))+1;--org_data<0，补码=|原码|取反+1。 END IF; END PROCESS; END BHV; 3—10 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity add is port(a:in std_logic_vector(7 downto 0); b:in std_logic_vector(7 downto 0); ci:in std_logic; co:out std_logic; count:out std_logic_vector(7 downto 0)); end add; architecture bhv of add is begin process(a,b,ci) variable data:std_logic_vector(1 downto 0); variable c:std_logic; begin c:=ci; for n in 0 to 7 loop data:=('0'&a(n))+('0'&b(n))+('0'&c); count(n)<=data(0); c:=data(1); end loop; co<=c; end process; end bhv; 3-14 用循环语句设计一个7人投票表决器，及一个4位4输入最大数值检测电路。 --解：5-7 用循环语句设计一个7人投票表决器，及一个4位4输出最大数值检测电路。 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY vote_7 IS PORT( DIN: IN STD_LOGIC_VECTOR(6 DOWNTO 0);--7位表决输入(1:同意，0:不同意) G_4: OUT STD_LOGIC; --超过半数指示 CNTH: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));--表决结果统计数 END vote_7; ARCHITECTURE BHV OF vote_7 IS BEGIN PROCESS(DIN)